On 29/06/2022 12:23, Chanho Park wrote: > Modern exynos SoCs such as Exynos Auto v9 have different internal clock > divider, for example "4". To support this internal value, this adds > clk_div of the s3c64xx_spi_port_config and assign "2" as the default > value to existing s3c64xx_spi_port_config. > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
Re: [PATCH v3 2/4] spi: s3c64xx: support custom value of internal clock divider
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- Subject: Re: [PATCH v3 2/4] spi: s3c64xx: support custom value of internal clock divider
- From: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
- Date: Wed, 29 Jun 2022 13:13:21 +0200
- Cc: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>, devicetree@xxxxxxxxxxxxxxx, linux-spi@xxxxxxxxxxxxxxx, linux-samsung-soc@xxxxxxxxxxxxxxx, linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
- In-reply-to: <20220629102304.65712-3-chanho61.park@samsung.com>
- References: <20220629102304.65712-1-chanho61.park@samsung.com> <CGME20220629102527epcas2p42e99f44d529d215623bd0e12a082d1dd@epcas2p4.samsung.com> <20220629102304.65712-3-chanho61.park@samsung.com>
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- References:
- [PATCH v3 0/4] spi support for Exynos Auto v9 SoC
- From: Chanho Park
- [PATCH v3 2/4] spi: s3c64xx: support custom value of internal clock divider
- From: Chanho Park
- [PATCH v3 0/4] spi support for Exynos Auto v9 SoC
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