On Mon, Jun 06, 2022 at 04:56:06PM +0530, Amit Kumar Mahapatra wrote:
> ---
> drivers/spi/spi-zynqmp-gqspi.c | 30 ++++++++++++++++++++++++++----
> drivers/spi/spi.c | 10 +++++++---
> include/linux/spi/spi.h | 10 +++++++++-
> 3 files changed, 42 insertions(+), 8 deletions(-)
Please split the core and driver support into separate patches, they are
separate things.
> --- a/drivers/spi/spi.c
> +++ b/drivers/spi/spi.c
> @@ -2082,6 +2082,8 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
> {
> u32 value;
> int rc;
> + u32 cs[SPI_CS_CNT_MAX];
> + u8 idx;
>
> /* Mode (clock phase/polarity/etc.) */
> if (of_property_read_bool(nc, "spi-cpha"))
This is changing the DT binding but doesn't have any updates to the
binding document. The binding code also doesn't validate that we don't
have too many chip selects.
> + /* Bit mask of the chipselect(s) that the driver
> + * need to use form the chipselect array.
> + */
> + u8 cs_index_mask : 2;
Why make this a bitfield?
I'm also not seeing anything here that checks that the driver supports
multiple chip selects - it seems like something that's going to cause
issues and we should probably have something to handle that situation.
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