Re: [PATCH 2/2] spi: cadence-quadspi: Add support for OSPI device reset

[Pratyush Yadav <p.yadav@xxxxxx>]

On 05/04/22 04:30PM, Sai Krishna Potthuri wrote:
> Cadence OSPI controller always start in SDR mode and it doesn't know
> the current mode of the flash device (SDR or DDR). This creates issue
> during Cadence OSPI driver probe if OSPI flash device is in DDR mode.
> This patch add OSPI flash device reset using HW reset pin for Xilinx
> Versal platform, this will make sure both Controller and Flash device
> are in same mode (SDR).

Is this supposed to reset the OSPI flash or the controller? If you are 
resetting it in the flash then you should handle this from the flash 
driver, not from here.

Also, as of now at least, SPI NOR only works when the flash is in SDR 
mode. For TI platforms, we reset the flash in the bootloader (U-Boot), 
before handing control off to the kernel. If you do want to properly 
handle flashes that are handed to the kernel in DDR mode, I would 
suggest you update SPI NOR instead to detect the flash mode and work 
from there. This would also allow us to support flashes that boot in DDR 
mode, so would still be in DDR mode even after a reset.

> Xilinx Versal platform has a dedicated pin used for OSPI device reset.
> As part of the reset sequence, configure the pin to enable
> hysteresis and set the direction of the pin to output before toggling
> the pin. Provided the required delay ranges while toggling the pin to
> meet the most of the OSPI flash devices reset pulse width, reset recovery
> and CS high to reset high timings.
> 
> Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xxxxxxxxxx>
[...]

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.