Re: [PATCH 0/4] spi-mem: Allow specifying the byte order in DTR mode

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Am 2022-02-22 14:54, schrieb Tudor.Ambarus@xxxxxxxxxxxxx:
On 2/21/22 09:44, Michael Walle wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe

Am 2022-02-18 15:58, schrieb Tudor Ambarus:
Fortunately there are controllers
that can swap back the bytes at runtime, fixing the endiannesses.
Provide
a way for the upper layers to specify the byte order in DTR mode.

Are there any patches for the atmel-quadspi yet? What happens if

not public, but will publish them these days.

the controller doesn't support it? Will there be a software fallback?

no need for a fallback, the controller can ignore op->data.dtr_bswap16 if
it can't swap bytes.

I don't understand. If the controller doesn't swap the 16bit values,
you will read the wrong content, no?

-michael



[Index of Archives]     [Linux Kernel]     [Linux ARM (vger)]     [Linux ARM MSM]     [Linux Omap]     [Linux Arm]     [Linux Tegra]     [Fedora ARM]     [Linux for Samsung SOC]     [eCos]     [Linux Fastboot]     [Gcc Help]     [Git]     [DCCP]     [IETF Announce]     [Security]     [Linux MIPS]     [Yosemite Campsites]

  Powered by Linux