Re: [PATCH] spi: cadence-quadspi: fix write completion support

[Pratyush Yadav <p.yadav@xxxxxx>]

On 08/11/21 02:08PM, Dinh Nguyen wrote:
> Some versions of the Cadence QSPI controller does not have the write
> completion register implemented(CQSPI_REG_WR_COMPLETION_CTRL). On the
> Intel SoCFPGA platform the CQSPI_REG_WR_COMPLETION_CTRL register is
> not configured.
> 
> Add a quirk to not write to the CQSPI_REG_WR_COMPLETION_CTRL register.
> 
> Fixes: 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling)
> Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx>
> ---
>  drivers/spi/spi-cadence-quadspi.c | 24 +++++++++++++++++++++---
>  1 file changed, 21 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
> index 8b3d268ac63c..b808c94641fa 100644
> --- a/drivers/spi/spi-cadence-quadspi.c
> +++ b/drivers/spi/spi-cadence-quadspi.c
> @@ -37,6 +37,7 @@
>  #define CQSPI_NEEDS_WR_DELAY		BIT(0)
>  #define CQSPI_DISABLE_DAC_MODE		BIT(1)
>  #define CQSPI_SUPPORT_EXTERNAL_DMA	BIT(2)
> +#define CQSPI_NO_SUPPORT_WR_COMPLETION	BIT(3)
>  
>  /* Capabilities */
>  #define CQSPI_SUPPORTS_OCTAL		BIT(0)
> @@ -86,6 +87,7 @@ struct cqspi_st {
>  	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
>  	bool			use_dma_read;
>  	u32			pd_dev_id;
> +	bool			wr_completion;

We have a bunch of bools lying around in this struct: is_decoded_cs, 
rclk_en, use_direct_mode, use_dma_read, and now wr_completion. It is 
probably worth it to use bitfields and save some memory.

Anyway, I don't consider this a blocker. So either way,

Reviewed-by: Pratyush Yadav <p.yadav@xxxxxx>

>  };
>  
>  struct cqspi_driver_platdata {
> @@ -996,9 +998,11 @@ static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
>  	 * polling on the controller's side. spinand and spi-nor will take
>  	 * care of polling the status register.
>  	 */
> -	reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
> -	reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
> -	writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
> +	if (cqspi->wr_completion) {
> +		reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
> +		reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
> +		writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
> +	}
>  
>  	reg = readl(reg_base + CQSPI_REG_SIZE);
>  	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
> @@ -1736,6 +1740,10 @@ static int cqspi_probe(struct platform_device *pdev)
>  
>  	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
>  	master->max_speed_hz = cqspi->master_ref_clk_hz;
> +
> +	/* write completion is supported by default */
> +	cqspi->wr_completion = true;
> +
>  	ddata  = of_device_get_match_data(dev);
>  	if (ddata) {
>  		if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
> @@ -1747,6 +1755,8 @@ static int cqspi_probe(struct platform_device *pdev)
>  			cqspi->use_direct_mode = true;
>  		if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA)
>  			cqspi->use_dma_read = true;
> +		if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION)
> +			cqspi->wr_completion = false;
>  
>  		if (of_device_is_compatible(pdev->dev.of_node,
>  					    "xlnx,versal-ospi-1.0"))
> @@ -1859,6 +1869,10 @@ static const struct cqspi_driver_platdata intel_lgm_qspi = {
>  	.quirks = CQSPI_DISABLE_DAC_MODE,
>  };
>  
> +static const struct cqspi_driver_platdata socfpga_qspi = {
> +	.quirks = CQSPI_NO_SUPPORT_WR_COMPLETION,
> +};
> +
>  static const struct cqspi_driver_platdata versal_ospi = {
>  	.hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
>  	.quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA,
> @@ -1887,6 +1901,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
>  		.compatible = "xlnx,versal-ospi-1.0",
>  		.data = (void *)&versal_ospi,
>  	},
> +	{
> +		.compatible = "intel,socfpga-qspi",
> +		.data = (void *)&socfpga_qspi,
> +	},
>  	{ /* end of table */ }
>  };
>  
> -- 
> 2.25.1
> 

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.