Hi Prabhakar,
> +#define RPCIF_PHYADD 0x0070 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
> +#define RPCIF_PHYWR 0x0074 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
Nice detailed research, thanks! Minor nit: Keep the sorting
alphabetical: D3, E3, V3M.
> +static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif *rpc)
> +{
> + u32 data;
> +
> + regmap_write(rpc->regmap, RPCIF_PHYWR, 0xa5390000);
> + regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000000);
> + regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
> + regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000022);
> + regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
> + regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000024);
> +
> + regmap_read(rpc->regmap, RPCIF_PHYCNT, &data);
> + regmap_write(rpc->regmap, RPCIF_PHYCNT, data | RPCIF_PHYCNT_CKSEL(3));
> + regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030);
> + regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032);
> +}
Still magic values here. Don't you have them explained in your Gen3
documentation? It is tables 62.16 and 62.17 in my versions.
Other than these, looks good.
Thanks,
Wolfram
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