From: Chris Morgan <macromorgan@xxxxxxxxxxx> Add a devicetree entry for the Rockchip SFC for the RK3036 SOC. Signed-off-by: Chris Morgan <macromorgan@xxxxxxxxxxx> Signed-off-by: Jon Lin <jon.lin@xxxxxxxxxxxxxx> --- Changes in v10: None Changes in v9: None Changes in v8: None Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None Changes in v1: None arch/arm/boot/dts/rk3036.dtsi | 42 +++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index e24230d50a78..06e37be81393 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -206,6 +206,17 @@ status = "disabled"; }; + sfc: spi@10208000 { + compatible = "rockchip,sfc"; + reg = <0x10208000 0x4000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; + pinctrl-names = "default"; + status = "disabled"; + }; + sdmmc: mmc@10214000 { compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; @@ -684,6 +695,37 @@ }; }; + sfc { + sfc_bus4: sfc-bus4 { + rockchip,pins = + <1 RK_PD0 3 &pcfg_pull_none>, + <1 RK_PD1 3 &pcfg_pull_none>, + <1 RK_PD2 3 &pcfg_pull_none>, + <1 RK_PD3 3 &pcfg_pull_none>; + }; + + sfc_bus2: sfc-bus2 { + rockchip,pins = + <1 RK_PD0 3 &pcfg_pull_none>, + <1 RK_PD1 3 &pcfg_pull_none>; + }; + + sfc_cs0: sfc-cs0 { + rockchip,pins = + <2 RK_PA2 3 &pcfg_pull_none>; + }; + + sfc_cs1: sfc-cs1 { + rockchip,pins = + <2 RK_PA3 3 &pcfg_pull_none>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = + <2 RK_PA4 3 &pcfg_pull_none>; + }; + }; + emac { emac_xfer: emac-xfer { rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */ -- 2.17.1