On Thu, Jun 03, 2021 at 09:34:21AM +0200, patrice.chotard@xxxxxxxxxxx wrote: > From: Patrice Chotard <patrice.chotard@xxxxxxxxxxx> > > In U-boot side, an issue has been encountered when QSPI source clock is > running at low frequency (24 MHz for example), waiting for TCF bit to be > set didn't ensure that all data has been send out the FIFO, we should also > wait that BUSY bit is cleared. Please remember to put the [PATCH] in your subject.
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