On Fri, May 07, 2021 at 12:48:27AM +0530, Pratyush Yadav wrote: > In 8D-8D-8D mode two bytes are transferred per cycle. So an odd number > of bytes cannot be transferred because it would leave a residual half > cycle at the end. Consider such a transfer invalid and reject it. > > Signed-off-by: Pratyush Yadav <p.yadav@xxxxxx> > > --- > This patch should go through the SPI tree but I have included it in this > series because if it goes in before patches 1-3, Micron MT35XU and > Cypress S28HS flashes will stop working correctly. It seems like this should probably even go in as a fix even if nothing is broken with mainline right now, it's the sort of thing some out of tree patch could easily trigger. Unless anyone objects I'll do that.
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