Hi, This series adds support for OSPI PHY calibration on the Cadence OSPI controller. This calibration procedure is needed to allow high clock speeds in 8D-8D-8D mode. The procedure reads some pre-determined pattern data from the flash and runs a sequence of test reads to find out the optimal delays for high speed transfer. More details on the calibration procedure in patch 5/6. The main problem here is telling the controller where to find the pattern and how to read it. This RFC uses nvmem cells which point to a fixed partition containing the data to do the reads. It depends on [0] and [1]. The obvious problem with this is it won't work when the partitions are defined via command line. I don't see any good way to add nvmem cells to command line partitions. I would like some help or ideas here. We don't necessarily have to use nvmem either. Any way that can cleanly and consistently let the controller find out where the pattern is stored is good. The dts patch depends on [2]. Tested on TI's J721E EVM. [0] https://patchwork.ozlabs.org/project/linux-mtd/patch/20210302190012.1255-1-zajec5@xxxxxxxxx/ [1] https://patchwork.ozlabs.org/project/linux-mtd/patch/20210308011853.19360-1-ansuelsmth@xxxxxxxxx/ [2] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210305153926.3479-2-p.yadav@xxxxxx/ Pratyush Yadav (6): spi: spi-mem: Tell controller when device is ready for calibration mtd: spi-nor: core: consolidate read op creation mtd: spi-nor: core: run calibration when initialization is done spi: cadence-qspi: Use PHY for DAC reads if possible spi: cadence-qspi: Tune PHY to allow running at higher frequencies arm64: dts: ti: k3-j721e-som-p0: Enable PHY calibration arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 55 ++ drivers/mtd/spi-nor/core.c | 74 +- drivers/spi/spi-cadence-quadspi.c | 820 +++++++++++++++++++- drivers/spi/spi-mem.c | 12 + include/linux/spi/spi-mem.h | 8 + 5 files changed, 916 insertions(+), 53 deletions(-) -- 2.30.0