Hello Andy. Have you tested the recent revision of the DW APB SSI driver with DMA enabled? I am particularly concerned about the next fix in the driver: > --- a/drivers/spi/spi-dw-dma.c > +++ b/drivers/spi/spi-dw-dma.c > @@ -346,8 +375,8 @@ static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer) > { > u16 imr = 0, dma_ctrl = 0; > > - dw_writel(dws, DW_SPI_DMARDLR, RX_BURST_LEVEL - 1); > - dw_writel(dws, DW_SPI_DMATDLR, TX_BURST_LEVEL); > + dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1); > + dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - dws->txburst); > > if (xfer->tx_buf) { > dma_ctrl |= SPI_DMA_TDMAE; Generally speaking it must work (even DW APB SSI/DMA databook suggests to have such DMATDLR setting), but in our case of a relatively slow DMA engine (it's clocked with just twice higher frequency with respect to the max SPI bus speed) sometimes SPI Rx FIFO gets overflown when SPI bus is configured to work with maximum speed (there are multiple reasons why this happens, but generally speaking all of them matter only due to the relatively slow DMA engine). The problem is fixed by reducing a value written into the DMATDLR register. I am wondering whether you've tested the last revision of the driver and it worked for your version of the DW APB SSI + DW DMAC IPs. AFAIU DMA engine on your devices is faster than on ours and has LLPs supported. So if you haven't noticed any problem in the recent driver, then I'll send a fixup for our version of the DW APB SSI block only (I'll have to introduce a new compatible string). Otherwise I could get back a setting of dws->txburst into the DW_SPI_DMATDLR register, which isn't that optimal as the current DMATDLR setting of (fifo_len - txburst), but at least will make things working for all DMAs. -Sergey