On 22/05/20 05:32PM, Boris Brezillon wrote: > On Fri, 22 May 2020 15:42:43 +0530 > Pratyush Yadav <p.yadav@xxxxxx> wrote: > > > In xSPI mode, flashes expect 2-byte opcodes. The second byte is called > > the "command extension". There can be 3 types of extensions in xSPI: > > repeat, invert, and hex. When the extension type is "repeat", the same > > opcode is sent twice. When it is "invert", the second byte is the > > inverse of the opcode. When it is "hex" an additional opcode byte based > > is sent with the command whose value can be anything. > > > > So, make opcode a 16-bit value and add a 'nbytes', similar to how > > multiple address widths are handled. > > A slightly different version of patch 5 should go before this patch, > otherwise your series is not bisectable. By slightly different, I mean > that you should only write one byte, but put this byte in a temporary > var. Or maybe you can squash patch 5 in this one and mention why you do > so in your commit message. How about the patch below before this patch? The supports_op() will reject multi-byte opcodes anyway, so we only care about single-byte opcodes for now. Multi-byte opcodes can be patched and tested later. This avoids squashing changes in this patch and having the changes split over two patches; one before and one after. -- 8< -- diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index 69491f3a515d..4e4292f0ee1d 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -356,6 +356,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, int nio = 1, i, ret; u32 ss_ctrl; u8 addr[8]; + u8 opcode = op->cmd.opcode & 0xff; ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz); if (ret) @@ -393,7 +394,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, mxic->regs + HC_CFG); - ret = mxic_spi_data_xfer(mxic, &op->cmd.opcode, NULL, 1); + ret = mxic_spi_data_xfer(mxic, &opcode, NULL, 1); if (ret) goto out; -- Regards, Pratyush Yadav