On 4/28/2020 7:30 PM, Hauke Mehrtens wrote:
On 4/28/20 1:10 PM, Daniel Schwierzeck wrote:
Am 24.04.20 um 12:42 schrieb Dilip Kota:
...
Hi,
The Interrupt controller found on Danube till xrx300 which is probably
from Infineon like this SPI controller IP acknowledges the interrupts
also inside this SPI controller IP automatically, this has to be done
manually on the xrx500 and probably also LGM as they use a different
interrupt controller. I prepared patches for this internally 2.5 years
ago but did not send them upstream because of internal processes.
I would suggest to only do this ack on the newer platforms starting with
the xrx500 and not on the older.
On SMP systems a lock is needed in lantiq_ssc_xmit_interrupt() to
protect against an other thread reading from the RX buffer or writing to
the TX buffer in parallel.
@Dilip. Did you try the patches I send you one months ago on the LGM?
All the cases you mentioned are taken care in the patch, could you
please have a look once.
And the patch you shared internally, has done below change. By referring
it i have updated the offsets, mentioning offsets are wrong. But actual
case is vrx200 are having different offsets and xrx500, latest chipsets
are having different offsets. I think this could be the reason for SPI
transfer timeouts when you run test on vrx200 with my patches.
-#define LTQ_SPI_IRNICR 0xf8
-#define LTQ_SPI_IRNCR 0xfc
+#define LTQ_SPI_IRNCR 0xf8
+#define LTQ_SPI_IRNICR 0xfc
These offsets need to be defined in SoC data structure as they are
different across the chipsets(which i have done in initial phase of the
patch which i submitted for internal review. I hope you had got a chance
to review it).
Regards,
Dilip
