Re: Execute spi transfers inside FIQ (NMI) or panic

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Am 26.02.2020 um 12:33 schrieb Mark Brown:
On Wed, Feb 26, 2020 at 08:36:37AM +0100, Herbrechtsmeier Dr.-Ing. , Stefan wrote:

I see two possible solutions.
a) The complexity is handled inside the client. The client uses the
controller exclusive and isn’t allowed to use the new panic transfer during
a normal transfer.
Then someone builds a system with two devices attached to a single SPI
controller...  besides, you've got no mechanism for controlling when a
kernel might panic or power might be lost.  I'm not sure a scheme that
relies on being able to control when stuff happens is going to be what
you need.

In my case this works because I read from the device during probe and write to the device during a panic or after power failure. But I understand that this isn't a generic solution.



[Index of Archives]     [Linux Kernel]     [Linux ARM (vger)]     [Linux ARM MSM]     [Linux Omap]     [Linux Arm]     [Linux Tegra]     [Fedora ARM]     [Linux for Samsung SOC]     [eCos]     [Linux Fastboot]     [Gcc Help]     [Git]     [DCCP]     [IETF Announce]     [Security]     [Linux MIPS]     [Yosemite Campsites]

  Powered by Linux