On 2/4/20 5:05 AM, Andy Shevchenko wrote:
On Tue, Feb 4, 2020 at 12:30 AM Eddie James <eajames@xxxxxxxxxxxxx> wrote:
There exists a set of SPI controllers on some POWER processors that may
be accessed through the FSI bus. Add a driver to traverse the FSI CFAM
engine that can access and drive the SPI controllers. This driver would
typically be used by a baseboard management controller (BMC).
The SPI controllers operate by means of programming a sequencing engine
which automatically manages the usual SPI protocol buses. The driver
programs each transfer into the sequencer as various operations
specifying the slave chip and shifting data in and out on the lines.
Some comments left unsettled in v1, thus applicable here.
I think I addressed all of Andy's comments on v1 now, if Andy agreed
about leaving the byte shifting as-is in fsi_spi_data_in/out.
Thanks,
Eddie
