On 13/01/2020 14:34, Andy Shevchenko wrote:
On Mon, Jan 13, 2020 at 02:27:54PM +0000, Mark Brown wrote:
On Mon, Jan 13, 2020 at 04:17:32PM +0200, Andy Shevchenko wrote:
On Mon, Jan 13, 2020 at 4:07 PM Mark Brown <broonie@xxxxxxxxxx> wrote:
On Mon, Jan 13, 2020 at 01:01:06PM +0000, John Garry wrote:
On 13/01/2020 11:42, Mark Brown wrote:
The idiomatic approach appears to be for individual board vendors
to allocate IDs, you do end up with multiple IDs from multiple
vendors for the same thing.
But I am not sure how appropriate that same approach would be for some 3rd
party memory part which we're simply wiring up on our board. Maybe it is.
It seems to be quite common for Intel reference designs to assign
Intel IDs to non-Intel parts on the board (which is where I
became aware of this practice).
Basically vendor of component in question is responsible for ID, but
it seems they simple don't care.
AFAICT a lot of the time it seems to be that whoever is writing
the software ends up assigning an ID, that may not be the silicon
vendor.
...which is effectively abusing the ACPI ID allocation procedure.
(And yes, Intel itself did it in the past — see badly created ACPI IDs
in the drivers)
Hi Mark,
About this topic of ACPI having no method to describe device buswidth in
the resource descriptor, it may be an idea for me to raise a Tianocore
feature request @ https://bugzilla.tianocore.org/
There seems to be an avenue there for raising new features for the spec.
I (or my org) can't participate in AWSG.
I would have no concrete proposal for spec update for now, though.
Hopefully others with more expertise could contribute.
In the meantime, I have an RFC for using DMI to quirk support for this
on the driver - I can share when ready.
Thanks,
John
