On Sat, Dec 28, 2019 at 04:31:53PM +0800, kongxinwei wrote: > > I'd be much more comfortable here if I understood what this was > > supposed to be syncing - what exactly gets flushed here and why > > is a memory barrier enough to ensure it's synced? A comment in > > the code would be especially good so anyone modifying the code > > understands this in future. > Because of out-of-order execution about some CPU architecture, > In this debug stage we find Completing spi interrupt enable -> > prodrucing TXEI interrupt -> running "interrupt_transfer" function > will prior to set "dw->rx and dws->rx_end" data, so it will result > in SPI sending error Could you update the commit message to say that, and ideally also add a comment saying something like "Ensure dw->rx and dw->rx_end are visible" please?
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