Re: [PATCH 1/3] TI QSPI: Fix fclk frequency

[Jean Pihet <jean.pihet@xxxxxxxxxxxxxx>]

Tony,

On Tue, Dec 10, 2019 at 10:02 PM Tony Lindgren <tony@xxxxxxxxxxx> wrote:
>
> * Jean Pihet <jean.pihet@xxxxxxxxxxxxxx> [191210 19:22]:
> > On Tue, Dec 10, 2019 at 6:03 PM Tony Lindgren <tony@xxxxxxxxxxx> wrote:
> > > Well can test again with the patch below to see if that is
> > > enough to make it work :)
> >
> > This patch works OK! The correct clock is in use by the driver. The
> > hwmod warning shows up at boot:
> > [    0.103567] omap_hwmod: qspi: no dt node
> > [    0.103599] ------------[ cut here ]------------
> > [    0.103639] WARNING: CPU: 0 PID: 1 at
> > arch/arm/mach-omap2/omap_hwmod.c:2414 _init.constprop.29+0x198/0x4a0
> > [    0.103654] omap_hwmod: qspi: doesn't have mpu register target base
>
> OK good to hear. That warning will go away when the legacy platform
> data is removed. So the patch needs to initially still keep the
> "ti,hwmods" property until we remove the legacy platform data.
Can the patch be submitted like it is now? If so I am preparing a v2 series.

>
> > Glad to help to get to the final solution, please let me know how I
> > can help on that.
>
> Well is this needed as a fix or can it wait for the v5.6 merge window?
It can wait since this is an improvement, not a bugfix. Does that sound good?

>
> If it's needed as a fix, some kind of description for the issue
> fixed is needed. Any ideas there?
>
> We know the right clock is not found by the driver, but I'm now
> wondering if this ever worked or has there been some bootloader
> dependency?
The motivation is to optimize the SPI transfer speed, especially for
the SPI flash devices.
With the current code if a 48MHz SPI clock is required, the effective
clock will be at a 16MHz frequency.
There is no bootloader dependency afaik, U-Boot uses a macro that
defines the fixed 48MHz of the PER clock.

This description comes in the patch desciption.

Thanks!

Regards,
Jean

>
> Regards,
>
> Tony