[PATCH] Allowing Xilinx's AXI Quad widths different than 8 bits on userspace

[Alvaro Gamez Machado <alvaro.gamez@xxxxxxxxxx>]

Hi,

We had a couple of days ago a nice discussion [1] about a patch that I sent
that was in need of clarification. I've taken into consideration all the
conversation and I believe this small series will manage my ultimate goal
(being able to use from user space a 32 bits wordwidth SPI slave with
Xilinx's AXI IP core) while being explained enough and through the proper
procedure.

I assume there may still need to be some discussion to go on with this, but
I thought it'd be clearer if we all had the code upfront in its current
state.

First patch documents the new device tree property, while the second one
implements it.

The third patch, that could be applied on its own regardless of the first
two, solves a bug that appears only in combination of spidev usage and a
master SPI device that does not support 8 bits as datawidth.

[1] I have not been able to find a link to the archives of linux-spi, sorry

Thanks,

Alvaro Gamez Machado (3):
  spi: xilinx: add description of new property xlnx,num-transfer-bits
  spi: xilinx: Add DT support for selecting transfer word width
  spi: set bits_per_word based on controller's bits_per_word_mask

 Documentation/devicetree/bindings/spi/spi-xilinx.txt | 4 +++-
 drivers/spi/spi-xilinx.c                             | 7 ++++++-
 drivers/spi/spi.c                                    | 2 ++
 3 files changed, 11 insertions(+), 2 deletions(-)

-- 
2.23.0