On Wed, Sep 11, 2019 at 12:15:30PM +0200, Lukas Wunner wrote:
> Commit 3bd7f6589f67 ("spi: bcm2835: Overcome sglist entry length
> limitation") amended the BCM2835 SPI driver with support for DMA
> transfers whose buffers are not aligned to 4 bytes and require more than
> one sglist entry.
You said in the cover letter that this was at the start of the
series but it's actually patch 4 (or patch 3 in terms of the
order they were sent), and in any case it was already applied so
I'm not clear why you're resending it. If there's any difference
from the previous version please send an incremental fix for it
instead.
The entire series has arrived but it looks like this in my inbox:
749 r T 09/11 Lukas Wunner (1.6K) [PATCH v2 00/10] Speed up SPI simplex t
750 N T 09/11 Lukas Wunner (4.0K) ├─>[PATCH v2 05/10] spi: bcm2835: Drop
751 N T 09/11 Lukas Wunner (3.5K) ├─>[PATCH v2 09/10] dmaengine: bcm2835:
752 N T 09/11 Lukas Wunner (3.6K) ├─>[PATCH v2 04/10] spi: bcm2835: Work
753 N T 09/11 Lukas Wunner ( 17K) ├─>[PATCH v2 07/10] spi: bcm2835: Speed
754 N T 09/11 Lukas Wunner (5.2K) ├─>[PATCH v2 06/10] spi: bcm2835: Cache
755 N T 09/11 Lukas Wunner (2.1K) ├─>[PATCH v2 02/10] dmaengine: bcm2835:
756 N T 09/11 Lukas Wunner (1.3K) ├─>[PATCH v2 01/10] dmaengine: bcm2835:
757 N T 09/11 Lukas Wunner (2.6K) ├─>[PATCH v2 03/10] spi: Guarantee cach
758 N T 09/11 Lukas Wunner (1.1K) ├─>[PATCH v2 08/10] dmaengine: bcm2835:
759 N T 09/11 Lukas Wunner (8.6K) └─>[PATCH v2 10/10] spi: bcm2835: Speed
which is really not good, the random ordering you're using when
you send things means that it's a hassle to even figure out that
I've got the entire series. Please look into what you're doing
here, other people's patch serieses don't have this problem so
there must be something unusual with your tooling.
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