On Sat, Aug 03, 2019 at 12:10:00PM +0200, Lukas Wunner wrote: > __spi_alloc_controller() uses a single allocation to accommodate struct > > Reverse the order. A forthcoming commit leverages this to grant DMA > access to driver-private data of the BCM2835 SPI master. That's just shuffling the problem around, the same issues will then apply to the controller struct and you'll take a performance penalty on architectures that don't like unaligned accesses. > An alternative approach would be to round up struct spi_controller to > cacheline size, at the expense of some wasted memory. That would seem more logical, or just do two alloacations. It's not like we allocate huge numbers of SPI controllers.
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