On Sat, Aug 24, 2019 at 03:38:16PM +0300, Vladimir Oltean wrote:
> On Thu, 22 Aug 2019 at 21:19, Mark Brown <broonie@xxxxxxxxxx> wrote:
> > On Sun, Aug 18, 2019 at 09:25:57PM +0300, Vladimir Oltean wrote:
> > > + if (!ctlr->ptp_sts_supported) {
> > > + list_for_each_entry(xfer, &mesg->transfers, transfer_list) {
> > > + xfer->ptp_sts_word_pre = 0;
> > > + ptp_read_system_prets(xfer->ptp_sts);
> > > + }
> > > + }
> > We can do better than this for controllers which use transfer_one().
> You mean I should guard this "if", and the one below, with "&&
> !ctlr->transfer_one"?
Yes, that'd make it a bit more obvious that the better handling
is there.
> > > + * @ptp_sts_supported: If the driver sets this to true, it must provide a
> > > + * time snapshot in @spi_transfer->ptp_sts as close as possible to the
> > > + * moment in time when @spi_transfer->ptp_sts_word_pre and
> > > + * @spi_transfer->ptp_sts_word_post were transmitted.
> > > + * If the driver does not set this, the SPI core takes the snapshot as
> > > + * close to the driver hand-over as possible.
> > A couple of issues here. The big one is that for PIO transfers
> > this is going to either complicate the code or introduce overhead
> > in individual drivers for an extremely niche use case. I guess
> > most drivers won't implement it which makes this a bit moot but
> > then this is a concern that pushes back against the idea of
> > implementing the feature.
> The concern is the overhead in terms of code, or runtime performance?
Both, yes.
> Arguably the applications that require deterministic latency are
> actually going to push for overall less overhead at runtime, even if
> that comes at a cost in terms of code size. The spi-fsl-dspi driver
> does not perform worse by any metric after this rework.
Determinalistic and fast are often note the same thing here,
sometimes it's better not to optimize if the optimization only
works some of the time for example.
> > The other is that it's not 100% clear what you're looking to
> > timestamp here - is it when the data goes on the wire, is it when
> > the data goes on the FIFO (which could be relatively large)? I'm
> > guessing you're looking for the physical transfer here, if that's
> > the case should there be some effort to compensate for the delays
> > in the controller?
> The goal is to timestamp the moment when the SPI slave sees word N of
> the data. Luckily the DSPI driver raises the TCF (Transfer Complete
> Flag) once that word has been transmitted, which I used to my
> advantage. The EOQ mode behaves similarly, but has a granularity of 4
> words. The controller delays are hence implicitly included in the
> software timestamp.
The documentation should be clear on that, it'd be very natural
for someone to timestamp on entry to the FIFO.
> But the question is valid and I expect that such compensation might be
> needed for some hardware, provided that it can be measured and
> guaranteed. In fact Hubert did add such logic to the v3 of his MDIO
> patch: https://lkml.org/lkml/2019/8/20/195 There were some objections
> mainly related to the certainty of those offset corrections. I don't
> want to "future-proof" the API now with features I have no use of, but
> such compensation logic might come in the future.
I think it's mainly important that people know what the
expectations are so different drivers are consistent in how they
work, as you say the API can always be extended later.
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