I have a logic analyzer that cannot sample signals at a higher frequency than this, and it's nice to actually see the captured data and not just an amorphous mess. Signed-off-by: Vladimir Oltean <olteanv@xxxxxxxxx> --- arch/arm/boot/dts/ls1021a-tsn.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts b/arch/arm/boot/dts/ls1021a-tsn.dts index 3b35e6b5977f..8fdf4c3b24c7 100644 --- a/arch/arm/boot/dts/ls1021a-tsn.dts +++ b/arch/arm/boot/dts/ls1021a-tsn.dts @@ -55,7 +55,7 @@ #size-cells = <0>; compatible = "nxp,sja1105t"; /* 12 MHz */ - spi-max-frequency = <12000000>; + spi-max-frequency = <6000000>; /* Sample data on trailing clock edge */ spi-cpha; /* SPI controller settings for SJA1105 timing requirements */ -- 2.17.1