RE: [PATCH 1/2] spi: pxa2xx: fix SCR (divisor) calculation

[Flavio Suligoi <f.suligoi@xxxxxxx>]

Hi Jarkko,

> > diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
> > index f7068cc..c9560a1 100644
> > --- a/drivers/spi/spi-pxa2xx.c
> > +++ b/drivers/spi/spi-pxa2xx.c
> > @@ -884,10 +884,15 @@ static unsigned int ssp_get_clk_div(struct
> driver_data *drv_data, int rate)
> >
> >   	rate = min_t(int, ssp_clk, rate);
> >
> > +	/*
> > +	 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
> > +	 * that the SSP transmission rate can be greater than the device
> rate
> > +	 */
> >   	if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
> > -		return (ssp_clk / (2 * rate) - 1) & 0xff;
> > +		return (ssp_clk / (2 * rate) - 1 +
> > +			(ssp_clk % (2 * rate) ? 1 : 0)) & 0xff;
> >   	else
> > -		return (ssp_clk / rate - 1) & 0xfff;
> > +		return (ssp_clk / rate - 1 + (ssp_clk % rate ? 1 : 0)) &
> 0xfff;
> >   }
> >
> I think DIV_ROUND_UP() - 1 would also fix this?
> 
> I realized we have also another issue here with the low rates.
> Calculated divider will underflow due masking with 0xff or 0xfff when
> the rate is low enough.
> 
> Would you want to fix that by setting the ctlr->min_speed_hz so that spi
> core can validate the rate? I'm asking since it goes well together with
> your fix. Maybe one patch setting the min_speed_hz and getting masking
> off from here and then another fixing the rate calculation.

Ok for the two separate patches, I prepare them as soon as I can.

Thanks,

Flavio