On Tue, Mar 26, 2019 at 10:56:45PM -0700, Sowjanya Komatineni wrote: > With SW CS, during transfer completion CS is de-asserted by writing the > default command1 register value to SPI_COMMAND1 register. With this both > mode and CS state are set at the same time and if current transfer mode > is different to default SPI mode and if mode change happens prior to CS > de-assert, clock polarity can change while CS is active before transfer > finishes. This is a bug fix so I'd expect it to be much earlier in the series before any of the new features.
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