On Thu, 2019-03-07 at 10:30 +0000, Mark Brown wrote: > On Wed, Mar 06, 2019 at 06:57:12PM +0000, Trent Piepho wrote: > > > High speed receive operations may be less likely to have issues > > with > > FIFO overflow when using DMA than when using PIO. > > The eCSPI appears to insert a 4 bit pause after each word in DMA > > mode, > > not done in PIO mode, which can make DMA transfers 50% slower than > > PIO. > > Wow, that's... innovative. If that's the case can't the decision > function for switching to DMA be tweaked to take into account slave > mode operation instead? Do you mean slave mode as in the imx being the spi slave and the external device the master? That's not being used here. Or do you mean spi mode, as in clock phase and polarity? I'm not sure if that matters or not, though it certainly could. I can give the other modes and try and see what they do. Certainly I've seen spi masters that do funny things with CS pulses between words in certain modes. This is what I see on the SPI clock in DMA mode, https://imagebin.ca/v/4WEkEnvsVSkq That gap after each byte should not be there and isn't in PIO mode.