On Sun, Feb 24, 2019 at 12:03:33PM +0100, kernel@xxxxxxxxxxxxxxxx wrote: > Some devices - like the mcp2517fd - have for example an internal PLL > based on an external clock. So during setup you have to use speed_hz > of <clock_hz> / 2 (or 4MHz at most) and only when PLL is in sync we > may be using speed_hz from the dt (or less if a module parameter is > used to limit ourselves further) > So the initial setup would not be able to help here - and every > bus controller would now be required to implement setup. > It also means open coding the calculations in each driver that > needs something like this. > Thus it is - imo - in the right location to support it in spi core. I agree, this feature makes sense to me.
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