Re: Move drivers/staging/mt7621-spi/spi-mt7621.c out of staging ?

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On 31.01.19 23:47, NeilBrown wrote:
On Thu, Jan 31 2019, Stefan Roese wrote:

On 31.01.19 13:29, Mark Brown wrote:
On Thu, Jan 31, 2019 at 11:01:16AM +0100, Stefan Roese wrote:

I'm wondering about the current status of the staging SPI driver
for the MIPS MT7621 (MT7628/88). Are there any plans to pull this
driver into "drivers/spi" soon? If not, what is blocking this
integration?

I've no idea what the status of this driver is, I don't think I've ever
heard of it before - if someone sends a patch I'll review it.  I think
staging drivers are supposed to have a TODO in there with known issues?

Yes, thanks. I'll take care of the TODO's and will send a patch to move
it out of staging for review.

Thanks,
Stefan
I had a quick look through..

#define SPI_BPW_MASK(bits) BIT((bits) - 1)

This is an odd use of the BIT macro, as we don't want a bit, we want a
mask.
I'd make that

#define SPI_BPW_MASK(bits) ((1 << (bits)) - 1)

As it turns out, SPI_BPW_MASK is already defined in
include/linux/spi/spi.h:

 #define SPI_BPW_MASK(bits) BIT((bits) - 1)

So I'll just remove this macro from this driver instead.
mt7621_spi_reset() contains some magic numbers.  Using named
constants would be better.

According to

http://ftp.mqmaker.com/WiTi/Docs/Software/MT7621_ProgrammingGuide_Preliminary_Platform.pdf

the SPI_MASTER register is
Bits:
  29-31  rs_slave_select - select the slave SPI device
  28     clk_mode is clock divisor is odd, then:
             0 - CLK is low longer
             1 - CLK is high longer
  16-27  rs_clk_sel (N)
               SPI clock frequencys is hclk/(N+2)
  11-15  cs_dsel_cnt
              "De-select time of SPI chip select is configured to occupy
              the number of cycles of AHB clock"
  10     full-duplex (doens't actually work)
  9      Interrupt enable
          (I tried using interrupt instead of busy-wait, and flash
          reading is much slower)
  8      spi_start_sel -  Interval between spi_cs_n and spi_sclk (3 or 6)
  7      spi_prefetch
  6      bidir_mode (doesn't work)
  5      cpha (clock phase??)
  4      cpol (clock polatity)
  3      lsb_first
  2      more_buf_mode (4+32 bytes, rather than 4 bytes of buffer)
  0-1    serial_mode
            0 standard serial
            1 dual serial
            3 quad serial
            4 reserved.

So the mt7621_spi_reset:
  selects slave 7, enables more_buf_mode, and disabled full_duplex.

Nothing else jumps out.
If you would take on a final clean up and submission, I would really
appreciate it.

Thanks for your suggestions. I'll send some new patches to update
the driver in staging first before moving (with code shown in the
patch) to drivers/spi.

Thanks,
Stefan



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