The patch spi-atmel: support inter-word delay has been applied to the spi tree at https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From 473a78a7bbeb7c77b81b596095f59ce4fbbd49dc Mon Sep 17 00:00:00 2001 From: Jonas Bonn <jonas@xxxxxxxxxxx> Date: Wed, 30 Jan 2019 09:40:05 +0100 Subject: [PATCH] spi-atmel: support inter-word delay If the SPI slave requires an inter-word delay, configure the DLYBCT register accordingly. Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference board). Signed-off-by: Jonas Bonn <jonas@xxxxxxxxxxx> Acked-by: Nicolas Ferre <nicolas.ferre@xxxxxxxxxxxxx> CC: Nicolas Ferre <nicolas.ferre@xxxxxxxxxxxxx> CC: Mark Brown <broonie@xxxxxxxxxx> CC: Alexandre Belloni <alexandre.belloni@xxxxxxxxxxx> CC: Ludovic Desroches <ludovic.desroches@xxxxxxxxxxxxx> CC: linux-spi@xxxxxxxxxxxxxxx CC: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx Signed-off-by: Mark Brown <broonie@xxxxxxxxxx> --- drivers/spi/spi-atmel.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index f53f0c5e63da..4954f0ab1606 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c @@ -1201,13 +1201,14 @@ static int atmel_spi_setup(struct spi_device *spi) csr |= SPI_BIT(CSAAT); /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs. - * - * DLYBCT would add delays between words, slowing down transfers. - * It could potentially be useful to cope with DMA bottlenecks, but - * in those cases it's probably best to just use a lower bitrate. */ csr |= SPI_BF(DLYBS, 0); - csr |= SPI_BF(DLYBCT, 0); + + /* DLYBCT adds delays between words. This is useful for slow devices + * that need a bit of time to setup the next transfer. + */ + csr |= SPI_BF(DLYBCT, + (as->spi_clk / 1000000 * spi->word_delay_usecs) >> 5); asd = spi->controller_state; if (!asd) { -- 2.20.1