On Tue, Jan 29, 2019 at 06:26:31PM +0000, OpenSource wrote:
This patch should really be split up into
> Was toggling the chip enable on each transfer, which results in a CS
> pulse. There should be only one CS pulse per message or most SPI
> chips will not processes the message as intended.
My understanding is that this is a hardware limitation which DesignWare
have refused to fix (Amazon have a modified version of the IP which is
supported upstream which fixes the behaviour). What are you doing to
fix this? Previously everyone has just controlled the chip select as a
GPIO to avoid having to deal with the limitations of the IP.
> +/* Program settings that the dw spi can't change during a message
> + * without pulsing CS */
> +static int dw_spi_prepare_message(struct spi_master *master,
> + struct spi_message *message)
> +{
> + struct spi_device *spi = message->spi;
> + struct dw_spi *dws = spi_master_get_devdata(master);
Same tab/space corruption issues here.
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