Hi Neil,
On 2018/12/13 16:55, Neil Armstrong wrote:
Hi Sunny,
On 13/12/2018 09:39, Sunny Luo wrote:
The SPICC controller in Meson-AXG SoC is capable of using
a linear clock divider to reach a much fine tuned range of clocks,
while the old controller only use a power of two clock divider,
result at a more coarse clock range.
This patch should definitely go before patch 1.
Would you please show the reason?
+ /* Set master mode and enable controller */
+ writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER,
+ spicc->base + SPICC_CONREG);
Please remove it from meson_spicc_prepare_message() now.
Yes, I moved it here and forgot remove it at prepare_message().
