On Tue, Aug 14, 2018 at 02:30:02PM +0530, dkota@xxxxxxxxxxxxxx wrote: > On 2018-08-10 22:16, Mark Brown wrote: > > On Fri, Aug 10, 2018 at 09:59:46PM +0530, dkota@xxxxxxxxxxxxxx wrote: > > > delay_usecs is for inter-transfer delays within a message rather than > > > after the initial chip select assert (it can be used to keep chip > > > select > > > asserted for longer after the final transfer too). Obviously this is > > > also something that shouldn't be configured in a driver specific > > > fashion. > > Hmmm ok, so you mean don't send these as controller_data, rather add > > new > > members to the spi_device struct ? > spi_cs_clk_delay -> Adds Delay from CS line toggle to Clock line toggle > spi_inter_words_delay -> Adds inter-word delay for each transfer. > Could you please provide more information on accommodating these > parameters in SPI core structures like spi_device or spi_transfer? Why > because these are very > specific to Qualcomm SPI GENI controller. I'm not sure what specific information you're looking for here - these things are not obviously specific to your controller, I'm even aware of other controllers which can do them. > If we define them in spi core framework structures, SPI Slave driver will > program and expect it in the SPI transfers. Sure.
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