On 04/19/18 19:53, Andy Shevchenko wrote:
Currently the 32-bit device address only is supported for DMA. However,
starting from Intel Sunrisepoint PCH the DMA address of the device FIFO
can be 64-bit.
Change the respective variable to be compatible with DMA engine
expectations, i.e. to phys_addr_t.
Fixes: 34cadd9c1bcb ("spi: pxa2xx: Add support for Intel Sunrisepoint")
Cc: Jarkko Nikula <jarkko.nikula@xxxxxxxxxxxxxxx>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
---
drivers/spi/spi-pxa2xx.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h
index 513ec6c6e25b..0ae7defd3492 100644
--- a/drivers/spi/spi-pxa2xx.h
+++ b/drivers/spi/spi-pxa2xx.h
@@ -38,7 +38,7 @@ struct driver_data {
/* SSP register addresses */
void __iomem *ioaddr;
- u32 ssdr_physical;
+ phys_addr_t ssdr_physical;
Nice catch! Sunrisepoint SPI PCI BAR indeed has BAR high register and
BAR low type bits indicate 64 address range even BAR high seems to 0 in
my test machines.
Have you seen a real issue with this? And more over, can this cause
memory corruption if DMA is writing into (ssp->phys_base + SSDR) &
0xFFFFFFFF? I don't know so well the DMA handshaking can it do so but
both points are valid reasons to queue the fix into linux-stable.
Reviewed-by: Jarkko Nikula <jarkko.nikula@xxxxxxxxxxxxxxx>
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