Re: Issue with spi_map_buf

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On Thu, Jan 25, 2018 at 03:47:54PM +0100, Maxime Chevallier wrote:

> The issue boils down to this (for the sake of clarity, I simplified the
> function by taking the following assumptions :

> - We work on a vmalloced buffer
> - max_seg_size < PAGE_SIZE
> - len > max_seg_size (len is size of the buffer we want to split)

...

> 	min = min_t(size_t,
> 		    len, desc_len - offset_in_page(buf));

> The 'min' variable computation seems incorrect when max_seg_size is less
> than PAGE_SIZE, in particular the "desc_len - offset_in_page(buf)",
> which should be something like "(len % PAGE_SIZE) - offset_in_page(buf)"

If I'm understanding you correctly the issue you're identifying here is
that we ignore max_seg_size here and instead just use PAGE_SIZE (you
don't explicitly say what you think is wrong so I might be missing
something here).

> Unfortunately, this start to be complex if we want to take all possible
> cases into account : If we want to split a buffer in segments, where
> some might cross page boundaries, how do we know how much sg elements
> will there be ?

> I thought about using something like  __sg_alloc_table_from_pages, but
> the "max_segment" parameter is expected to be page aligned, which is not
> the case here.

Perhaps I'm missing something here but surely we just need to handle the
case where desc_len is bigger than offset_in_page()?  The number of
scatterlist entries we're going to need is at most DIV_ROUND_UP(PAGE_SIZE /
max_seg_size) * DIV_ROUND_UP(len / PAGE_SIZE) (ie, the number of
segments we need per page multiplied by the number of pages covered by
the data) which it looks like we already have mostly handled.

> I found this issue with a prototype implementation of SPI DMA xfers on
> armada 3700, using fpga-pgr as a spi device. In my case, max_seg_size is
> set to 512 bytes.

Like I say I might be missing something here.

> This should occur with other DMA / SPI controllers, as long as the
> max_seg_size is less than PAGE_SIZE.

I'm not sure how likely that is TBH - 512 is an extremely low limit for
a DMA controller.

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