Re: [PATCH] spi: orion: Allow specifying which HW CS to use with a GPIO CS

[Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>]

Hi Jan,

On Tue, Jan 23, 2018 at 8:56 PM, Jan Kundrát <jan.kundrat@xxxxxxxxx> wrote:
> Commit b28b9149b37f added support for using an additional GPIO pin for
> Chip Select. According to that commit and to my understanding of a
> semi-public datahseet, it seems that the SPI hardware really insists on
> driving *some* HW CS signal whenever a SPI transaction is in progress.
>
> The old code effectively forced the HW CS pin to be CS0. That means that
> there could not be anything connected to the real CS0 signal when one
> uses a GPIO CS. That assumption does not hold on e.g. Solidrun Clearfog
> where some SOM models have a built-in SPI flash on SPI1, CS0.
>
> Signed-off-by: Jan Kundrát <jan.kundrat@xxxxxxxxx>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/spi/spi-orion.txt
> +++ b/Documentation/devicetree/bindings/spi/spi-orion.txt
> @@ -28,6 +28,11 @@ Optional properties:
>  - clock-names : names of used clocks, mandatory if the second clock is
>                 used, the name must be "core", and "axi" (the latter
>                 is only for Armada 7K/8K).
> +- orion-spi,cs-gpio-hw-cs : Because the SoC always wants to drive some HW Chip
> +                           Select pin, it is necessary to specify which one
> +                           should be used when Linux drives an additional
> +                           GPIO as a software-controlled CS. Defaults to HW
> +                           CS 0.

Can't you just deduce an unused HW CS from the cs-gpios property?

Renesas MSIOF also requires driving a native chip select, cfr. commit
b8761434bdec32fa ("spi: sh-msiof: Implement cs-gpios configuration").

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

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when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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