RE: [PATCHv3 2/2] bindings: spi: Add clock entries for spi-xilinx

[Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxxxxx>]

> -----Original Message-----
> From: Lars-Peter Clausen [mailto:lars@xxxxxxxxxx]
> Sent: Thursday, March 10, 2016 6:10 PM
> To: Shubhrajyoti Datta; linux-spi@xxxxxxxxxxxxxxx
> Cc: Soren Brinkmann; devicetree@xxxxxxxxxxxxxxx; Michal Simek;
> broonie@xxxxxxxxxx; Shubhrajyoti Datta
> Subject: Re: [PATCHv3 2/2] bindings: spi: Add clock entries for spi-xilinx
> 
> On 03/10/2016 01:11 PM, Shubhrajyoti Datta wrote:
> [...]
> > @@ -7,6 +7,9 @@ Required properties:
> >  - interrupts		: Property with a value describing the interrupt
> >  			  number.
> >  - interrupt-parent	: Must be core interrupt controller
> > +- clocks: Input clock specifier. Refer to common clock bindings.
> > +- clock-names: tuple listing input clock names.
> > +	Required elements: "spi_fclk"
> 
> Sorry for being pedantic, but the core has two clock input "" and
> "ext_spi_clk". Which one is "spi_fclk"?

However for all my designs I adhere to the recommendation see below both are from the same clock source.
I  named it spi_fclk.

Do you think I should have 2 clocks requests on the same clock.


http://www.xilinx.com/support/documentation/ip_documentation/axi_quad_spi/v2_00_a/ds843_axi_quad_spi.pdf

page 12

15. It is recommended that the AXI4 interface clock and EXT_SPI_CLK clock originate from the same clock source.
> 
> - Lars

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