Stephan Olbrich <stephanolbrich@xxxxxx> writes: > From: Stephan Olbrich <stephanolbrich@xxxxxx> > > This patch series has some improvements and fixes for the auxiliary spi. > > since v1: > - the first two patches "fix bitmask defines" and "disable tx fifo empty irq" > were picked up by Mark Brown and applied to his spi tree so I don't post > them again. > - speed bits are now reset before setting the new speed in case the speed > changes between transfers > - remove CPHA from master->mode_bits > - rename CPHA bit mask to RISING to make it more clear why things are done > that way > > 1. set up spi-mode before asserting cs-gpio > As Martin Sperl suggested this is done in the same way as in spi-bcm2835.c > acace73df2c1913a526c1b41e4741a4a6704c863 > > 2. fix CPOL/CPHA setting > From what I've seen in the documentation [1] and seen on the scope this chip > doesn't support modes with CPHA=1. With this patch spi mode 0 and 2 should > work correctly whereas mode 1 and 3 are not supported. These are both: Reviewed-by: Eric Anholt <eric@xxxxxxxxxx> Thanks!
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