On Wed, Feb 10, 2016 at 02:04:21PM +0100, Rafał Miłecki wrote: > On 10 February 2016 at 13:48, Mark Brown <broonie@xxxxxxxxxx> wrote: > > It's most likely just hammering the CPU for a very long time without > > scheduling due to doing a long PIO transfers. That change just removes > > some needless context switching. > The fact is it happens only after flashing firmware, when flash is > formatted for the first time. After flashing some changes from ramfs > are likely flushed to the falsh. I guess it matches your theory of > long time CPU hammering. I bet you can trigger it with a heavy read load too (especially lots of reads going on in parallel). You'll have always been able to trigger it, it's just that this has made it easier. > Any idea how to handle this? Don't busy wait in the driver, ideally implement DMA support. Add some sleeps if you really need to. A PIO driver really isn't fit for purpose with large transfers like you get on flash.
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