On Wed, Jan 06, 2016 at 08:45:38AM +0700, Khoa Dang Pham wrote: > Hi Mark, Please don't top post, reply in line with needed context. This allows readers to readily follow the flow of conversation and understand what you are talking about and also helps ensure that everything in the discussion is being addressed. > According to the "DesignWare DW_apb_ssi Databook" (version 3.21b) provided > by Synopsys, the EEPROM read is: > "When TMOD = 2‘b11, the transmit data is used to transmit an opcode and/or > an address to the EEPROM > device. Typically this takes three data frames (8-bit opcode followed by > 8-bit upper address and 8-bit lower > address). During the transmission of the opcode and address, no data is > captured by the receive logic (as > long as the DW_apb_ssi master is transmitting data on its txd line, data on > the rxd line is ignored). The This is just a normal data transfer, if the driver is functioning correctly this should not be required and requiring it would mean that we'd need to go round adding workarounds for this to lots of client drivers. It seems like you are trying to work around some other bug in the driver, quite possibly incorrect handling of chip select as was suggested elsewhere. If that is the case a common solution is to manage the chip select as a GPIO rather than with the built in handling in the block if the block can't cope.
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