Re: [PATCH v4 4/5] ARM: dts: DRA7: add entry for qspi mmap region

[Tony Lindgren <tony@xxxxxxxxxxx>]

* Vignesh R <vigneshr@xxxxxx> [151129 21:16]:
> Add qspi memory mapped region entries for DRA7xx based SoCs. Also,
> update the binding documents for the controller to document this change.
> 
> Acked-by: Rob Herring <robh@xxxxxxxxxx>
> Signed-off-by: Vignesh R <vigneshr@xxxxxx>
...
> --- a/Documentation/devicetree/bindings/spi/ti_qspi.txt
> +++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
> @@ -26,3 +26,17 @@ qspi: qspi@4b300000 {
>  	spi-max-frequency = <25000000>;
>  	ti,hwmods = "qspi";
>  };
> +
> +For dra7xx:
> +qspi: qspi@4b300000 {
> +	compatible = "ti,dra7xxx-qspi";
> +	reg = <0x4b300000 0x100>,
> +	      <0x5c000000 0x4000000>,
> +	      <0x4a002558 0x4>;
> +	reg-names = "qspi_base", "qspi_mmap",
> +		    "qspi_ctrlmod";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	spi-max-frequency = <48000000>;
> +	ti,hwmods = "qspi";
> +};

Actually none of the IO areas above are within the same interconnect target:

0x4b300000  QSPI0 address space in L3 main interconnect
0x5c000000  QSPI1 address space in L3 main interconnect
0x4a002558  CTRL_CORE_CONTROL_IO_2 in System Control Module (SCM) in L4_CFG

The first two address spaces should be two separate instances of this driver.
The CTRL_CORE_CONTROL_IO_2 needs seems like a shared clock register that
needs to be accessed using the clock framework most likely.

So not applying, this will be impossible to move to some real interconnect
driver until these issues are fixed.

Regards,

Tony
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