On 06/10/2015 03:18 AM, Murali Karicheri wrote:
SPI hardware spec for Keystone specifies a lower value of 0 for pre-scale
divider that is used for generating spi clock which translates to a
clock divider of 2. So fix the lower limit to allow using a higher SPI
clock.
Signed-off-by: Murali Karicheri <m-karicheri2@xxxxxx>
Acked-by: Sekhar Nori <nsekhar@xxxxxx>
---
drivers/spi/spi-davinci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index 5e99106..987afeb 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -265,7 +265,7 @@ static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
- if (ret < 3 || ret > 256)
+ if (ret < 1 || ret > 256)
return -EINVAL;
return ret - 1;
Please ignore this as I messed up the PATCH prefix. I will re-send it
with v1 and some updates to the commit log.
--
Murali Karicheri
Linux Kernel, Keystone
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