On 2015-04-07 18:28, Mark Brown wrote:
On Tue, Apr 07, 2015 at 09:39:03AM -0600, Stephen Warren wrote:
On 04/07/2015 12:25 AM, Martin Sperl wrote:
... then not touch any CS-related register for the entire transfer. There
shouldn't be a need to enable/disable IRQs during the transfer; just leave
them enabled the entire time, until all bytes have been transferred.
We will need to make sure /CS is kept asserted between transfers in a
message too.
The problem is here that you need to touch the CS-register when an
individual spi-transfer is finished, as only that way you can disable
the (level)interrupts, which would fire immediately again when you exit
chip-select.
So you are at the risk of it happening at that phase as well...
and during the next spi_transfer_one you need to reenable the
interrupts again.
Anyway: my latest incarnation of the driver does now implement full
cs_gpio operation with native-cs getting translated during the
new spi_register_cs phase when registering the bus using the (new)
function-pointer register_cs in spi_master.
So this issue goes away and the code becomes smaller at the same time.
This is also used to set up chip_selects to their defaults levels prior
to any activity on the SPI bus.
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