Re: [PATCH 3/6] spi: bcm2835: fill FIFO before enabling interrupts to

[Martin Sperl <kernel@xxxxxxxxxxxxxxxx>]

> On 07.04.2015, at 19:40, Mark Brown <broonie@xxxxxxxxxx> wrote:
> 
> For your workload perhaps.  For some workloads they are very common
> (register reads are the most obvious example, they are typically a write
> transfer to provide the register address followed by a read transfer for
> the data).
Which spi_write_then_read collapses into a single transfer.

Still I try to run now 4 distinct devices for my testing and
I believe the enc28j60 is one of those devices that does that
and I have not seen an issue there during typical loads...
Obviously there are some devices that are easier to load than
others to trigger such a situation.

It really just shows when running some transfers a lot of times...

So the move to gpio-cs should be on our priority list.

I will come up with a generic approach that allows also to set native
CS if needed... (as sketched in an earlier mail)

Martin

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