On Fri, Apr 03, 2015 at 01:39:31PM -0700, Aaron Brice wrote: > Add delay between chip select and clock signals, before clock starts and > after clock stops. Applied, thanks.
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Re: [PATCH v3 3/3] spi: fsl-dspi: Add ~50ns delay between cs and sck
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- Subject: Re: [PATCH v3 3/3] spi: fsl-dspi: Add ~50ns delay between cs and sck
- From: Mark Brown <broonie@xxxxxxxxxx>
- Date: Mon, 6 Apr 2015 18:12:52 +0100
- In-reply-to: <1428093571-20407-4-git-send-email-aaron.brice@datasoft.com>
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- [PATCH v3 0/3] spi: fsl-dspi (vf610) clock fixes
- From: Aaron Brice
- [PATCH v3 3/3] spi: fsl-dspi: Add ~50ns delay between cs and sck
- From: Aaron Brice
- [PATCH v3 0/3] spi: fsl-dspi (vf610) clock fixes
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