[PATCH v2 0/2] spi: fsl-dspi (vf610) clock fixes

[Aaron Brice <aaron.brice@xxxxxxxxxxxx>]

We were having intermittent problems writing to SRAM chip on SPI bus on vf610
SoM.  Added support for CS setup and hold times to meet the SRAM spec.  In the
process noticed that the baud rate was a little high.

Changes since v1:
 * More detail in commit message for clock rate fix

Aaron Brice (2):
  spi: fsl-dspi: Fix clock rate scale values
  spi: fsl-dspi: Add ~50ns delay between cs and sck

 drivers/spi/spi-fsl-dspi.c | 84 ++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 70 insertions(+), 14 deletions(-)

-- 
2.1.0

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