On Sat, Aug 02, 2014 at 11:09:09AM +0200, Geert Uytterhoeven wrote: > On Sat, Aug 2, 2014 at 4:06 AM, Brian Norris > > On Wed, Jul 30, 2014 at 11:46:07AM +0100, Mark Brown wrote: > >> I don't know what DDR is in this context, sorry. > > I think it's just the ability to latch data on both the rising and > > falling edges of the SPI clock. For SPI flash, it seems to be used for > > the data portion of the opcode/address/data sequence. > > Yeah, I suppose it could be wedged in later if drivers/spi/ ever adopts > > a solution. > I think this can just be another SPI_* spi_device.mode flag. Sounds like it yes - I was wondering if this might be one of the modes with extra clock cycles that I've heard mentioned before which might be a little more fun. > Do we need bindings for this in > Documentation/devicetree/bindings/spi/spi-bus.txt? > Unlike Quad SPI transfer support, this doesn't need special wiring, so DDR > capability is an intrinsic property of the SPI slave, and the mode bit can just > be set in the SPI slave driver, without any DT magic? Right, unless we run into things like board design issues causing constraints this is something that can be enabled by the two drivers without needing DT configuration.
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