On Wed, Feb 12, 2014 at 03:29:05PM +0800, Chao Fu wrote: > From: Chao Fu <B44548@xxxxxxxxxxxxx> > > Freescale DSPI module will have two endianess in different platform, > but ARM is little endian. So when DSPI in big endian, core in little endian, > readl and writel can not adjust R/W register in this condition. > This patch will remove general readl/writel, and import regmap mechanism. > Data endian will be transfered in regmap APIs. Applied both, thanks.
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