Quoting Douglas Anderson (2020-10-14 17:13:29)
> From: Taniya Das <tdas@xxxxxxxxxxxxxx>
>
> In the case where the PLL configuration is lost, then the pm runtime
> resume will reconfigure before usage.
Taniya, this commit needs a lot more describing than one sentence. I see
that the PLL's L value is reset at boot, but only once. That seems to be
because the bootloader I have doesn't set bit 11 for the RETAIN_FF bit
on the lpass_core_hm_gdsc. Once the gdsc is turned off the first time,
the PLL settings are lost and the L val is reset to 0. That makes sense
because RETAIN_FF isn't set. This also means the other register writes
during probe are lost during the first suspend of the lpass core clk
controller. Then when the GDSC is turned on the next time for this clk
controller being runtime resumed we will set the retain bit and then
configure the PLL again. BTW, I see that runtime PM is called for this
clk controller for all the clk operations. Maybe there should be some
auto suspend timeout so that we're not toggling the gdsc constantly?
I hacked up the GDSC code to set the bit at gdsc registration time and
it seems to fix the problem I'm seeing (i.e. that the PLL is stuck,
which should also be in the commit text here). When I try to set the bit
in the bootloader though my kernel won't boot. I guess something is
hanging the system if I enable the retain bit in the GDSC?
>
> Fixes: edab812d802d ("clk: qcom: lpass: Add support for LPASS clock controller for SC7180")
> Signed-off-by: Taniya Das <tdas@xxxxxxxxxxxxxx>
> Signed-off-by: Douglas Anderson <dianders@xxxxxxxxxxxx>
