Quoting Taniya Das (2020-05-17 03:04:19)
> There is a requirement to support 51.2MHz from GPLL6 for qup clocks,
> thus update the frequency table and parent data/map to use the GPLL6
> source PLL.
>
> Fixes: 17269568f7267 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180")
> Signed-off-by: Taniya Das <tdas@xxxxxxxxxxxxxx>
> ---
Applied to clk-next
