Re: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks

[Taniya Das <tdas@xxxxxxxxxxxxxx>]

Hello Stephen,

On 10/10/2018 2:04 AM, Stephen Boyd wrote:
> Quoting Taniya Das (2018-10-09 06:57:47)
> > diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c
> > index 0cc4909..6d3136a 100644
> > --- a/drivers/clk/qcom/dispcc-sdm845.c
> > +++ b/drivers/clk/qcom/dispcc-sdm845.c
> > @@ -128,6 +144,100 @@ enum {
> >          },
> >   };
> >
> > +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
> > +       F(19200000, P_BI_TCXO, 1, 0, 0),
> > +       { }
> > +};
> > +
> > +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
> > +       .cmd_rcgr = 0x219c,
> > +       .mnd_width = 0,
> > +       .hid_width = 5,
> > +       .parent_map = disp_cc_parent_map_2,
> > +       .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
> > +       .clkr.hw.init = &(struct clk_init_data){
> > +               .name = "disp_cc_mdss_dp_aux_clk_src",
> > +               .parent_names = disp_cc_parent_names_2,
> > +               .num_parents = 2,
> > +               .flags = CLK_SET_RATE_PARENT,
> > +               .ops = &clk_rcg2_ops,
> > +       },
> > +};
> > +
> > +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = {
> > +       F(108000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),
> > +       F(180000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),
> > +       F(360000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),
> > +       F(540000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),
> > +       { }
> > +};
> > +
> > +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
> > +       .cmd_rcgr = 0x2154,
> > +       .mnd_width = 0,
> > +       .hid_width = 5,
> > +       .parent_map = disp_cc_parent_map_1,
> > +       .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src,
> > +       .clkr.hw.init = &(struct clk_init_data){
> > +               .name = "disp_cc_mdss_dp_crypto_clk_src",
> > +               .parent_names = disp_cc_parent_names_1,
> > +               .num_parents = 4,
> > +               .flags = CLK_GET_RATE_NOCACHE,
>
> Why?
>
> > +               .ops = &clk_rcg2_ops,
> > +       },
> > +};
> > +
> > +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = {
> > +       F(162000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),
> > +       F(270000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),
> > +       F(540000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),
> > +       F(810000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),
>
> Are these in kHz? They really look like it and that's bad. Why do we
> need them at all? Just to make sure the display driver picks these exact
> frequencies? It seems like we could just pass whatever number comes in
> up to the parent and see what it can do.

Let me check back the reason we had to make this change.

> > +       { }
> > +};
> > +
> > +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
> > +       .cmd_rcgr = 0x2138,
> > +       .mnd_width = 0,
> > +       .hid_width = 5,
> > +       .parent_map = disp_cc_parent_map_1,
> > +       .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src,
> > +       .clkr.hw.init = &(struct clk_init_data){
> > +               .name = "disp_cc_mdss_dp_link_clk_src",
> > +               .parent_names = disp_cc_parent_names_1,
> > +               .num_parents = 4,
> > +               .flags = CLK_SET_RATE_PARENT,
> > +               .ops = &clk_rcg2_ops,
> > +       },
> > +};
> > +
> > +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
> > +       .cmd_rcgr = 0x2184,
> > +       .mnd_width = 16,
> > +       .hid_width = 5,
> > +       .parent_map = disp_cc_parent_map_1,
> > +       .clkr.hw.init = &(struct clk_init_data){
> > +               .name = "disp_cc_mdss_dp_pixel1_clk_src",
> > +               .parent_names = disp_cc_parent_names_1,
> > +               .num_parents = 4,
> > +               .flags = CLK_SET_RATE_PARENT,
> > +               .ops = &clk_dp_ops,
> > +       },
> > +};
> > +
> > +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
> > +       .cmd_rcgr = 0x216c,
> > +       .mnd_width = 16,
> > +       .hid_width = 5,
> > +       .parent_map = disp_cc_parent_map_1,
> > +       .clkr.hw.init = &(struct clk_init_data){
> > +               .name = "disp_cc_mdss_dp_pixel_clk_src",
> > +               .parent_names = disp_cc_parent_names_1,
> > +               .num_parents = 4,
> > +               .flags = CLK_SET_RATE_PARENT,
> > +               .ops = &clk_dp_ops,
> > +       },
> > +};
> > +
> >   static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
> >          F(19200000, P_BI_TCXO, 1, 0, 0),
> >          { }
> > @@ -391,6 +501,115 @@ enum {
> >          },
> >   };
> >
> > +static struct clk_branch disp_cc_mdss_dp_aux_clk = {
> > +       .halt_reg = 0x2054,
> > +       .halt_check = BRANCH_HALT,
> > +       .clkr = {
> > +               .enable_reg = 0x2054,
> > +               .enable_mask = BIT(0),
> > +               .hw.init = &(struct clk_init_data){
> > +                       .name = "disp_cc_mdss_dp_aux_clk",
> > +                       .parent_names = (const char *[]){
> > +                               "disp_cc_mdss_dp_aux_clk_src",
> > +                       },
> > +                       .num_parents = 1,
> > +                       .flags = CLK_SET_RATE_PARENT,
> > +                       .ops = &clk_branch2_ops,
> > +               },
> > +       },
> > +};
> > +
> > +static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
> > +       .halt_reg = 0x2048,
> > +       .halt_check = BRANCH_HALT,
> > +       .clkr = {
> > +               .enable_reg = 0x2048,
> > +               .enable_mask = BIT(0),
> > +               .hw.init = &(struct clk_init_data){
> > +                       .name = "disp_cc_mdss_dp_crypto_clk",
> > +                       .parent_names = (const char *[]){
> > +                               "disp_cc_mdss_dp_crypto_clk_src",
> > +                       },
> > +                       .num_parents = 1,
> > +                       .flags = CLK_SET_RATE_PARENT,
> > +                       .ops = &clk_branch2_ops,
> > +               },
> > +       },
> > +};
> > +
> > +static struct clk_branch disp_cc_mdss_dp_link_clk = {
> > +       .halt_reg = 0x2040,
> > +       .halt_check = BRANCH_HALT,
> > +       .clkr = {
> > +               .enable_reg = 0x2040,
> > +               .enable_mask = BIT(0),
> > +               .hw.init = &(struct clk_init_data){
> > +                       .name = "disp_cc_mdss_dp_link_clk",
> > +                       .parent_names = (const char *[]){
> > +                               "disp_cc_mdss_dp_link_clk_src",
> > +                       },
> > +                       .num_parents = 1,
> > +                       .flags = CLK_SET_RATE_PARENT,
> > +                       .ops = &clk_branch2_ops,
> > +               },
> > +       },
> > +};
> > +
> > +/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */
>
> Not sure what this comment is for. But it's interesting nonetheless.
>
> > +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
> > +       .halt_reg = 0x2044,
> > +       .halt_check = BRANCH_HALT,
> > +       .clkr = {
> > +               .enable_reg = 0x2044,
> > +               .enable_mask = BIT(0),
> > +               .hw.init = &(struct clk_init_data){
> > +                       .name = "disp_cc_mdss_dp_link_intf_clk",
> > +                       .parent_names = (const char *[]){
> > +                               "disp_cc_mdss_dp_link_clk_src",
> > +                       },
> > +                       .num_parents = 1,
> > +                       .flags = CLK_GET_RATE_NOCACHE,
>
> Why?

It was a requirement, but let me get back on this too.

> > +                       .ops = &clk_branch2_ops,
> > +               },
> > +       },
> > +};
> > +

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